An important process during the fabrication of integrated circuits for semiconductor devices is formation of metal interconnects that provide electrical paths between conductive layers. Metal interconnects consist of trenches that provide horizontal connections between conductive features and via or contact holes that provide vertical connections between metal layers. These metal lines are separated by insulating or dielectric materials to prevent capacitance coupling or crosstalk between the metal wiring. Recent improvements in dielectric layers have involved replacing SiO2 that has a dielectric constant (k) of about 4 with a low k material such as carbon doped SiO2 or fluorine doped SiO2 that has a k value of close to 2. The low k dielectric material has an improved insulating capability that is especially needed as the dimension between wiring shrinks in newer devices.
Another means of reducing the k value of a dielectric material is described in U.S. Pat. No. 6,319,858 where pores or air pockets are produced in the surface of inorganic materials deposited by a CVD method or in purely organic layers such as polyimides. An inert gas like CO2, N2, He, Ar, or ethylene is applied at high pressure such that the gas permeates into the dielectric layer and the pressure is then quickly released at a reduction rate of between 5 to 110 psi/second. For a 2000 Angstrom thick Si—O—C—F layer, pores with a 5 to 80 nm diameter are formed and the k value decreases from 2.5–2.8 to a range of 2.2 to 2.6.
A popular interconnect structure is produced by a damascene technique in which an opening such as a via hole 14 shown in FIG. 1 is etched in a stack comprised of a top etch stop layer 13, a middle dielectric layer 12, and a bottom etch stop layer 11 that has been deposited on a substrate 9. Substrate 9 is comprised of at least one conductive layer 10 in a dielectric layer (not shown). The hole pattern is initially formed in a photoresist layer (not shown) that serves as an etch mask for the pattern transfer. Optionally, an anti-reflective layer or ARL (not shown) is inserted between the photoresist and etch stop 13 to improve the process latitude of the pattern forming step.
In FIG. 2, a barrier metal layer 15 is deposited in hole 14 by a CVD method followed by deposition of a metal 16 to fill the hole. Barrier layer 15 protects metal 16 from traces of water or other chemicals contained in adjacent layers 12, 13. A chemical mechanical polish (CMP) step is subsequently used to lower the level of metal 16 and remove the horizontal portion of barrier layer 15 so that the metal 16 becomes coplanar with etch stop 13.
One problem associated with the damascene process is that etch stop layer 13 which is typically a low k material like silicon carbide or PbO does not have good adhesion to the ARL in the patterning step or to metal barrier layer 15. As a result, various types of defects occur that degrade device performance. A void 17 is shown that results from a lack of adhesion of dielectric layer 13 to barrier layer 15. Void 17 induces stress in the adjacent barrier layer which in turn causes a stress in the metal layer 16. This can lead to defects such as scratches in etch stop 13 or even in dielectric layer 12. If the defects are detected before further process steps, the substrate can be reworked but this adds considerable expense to the fabrication scheme. Even if etch stop layer 13 is omitted, low k dielectric layer 12 has poor adhesion to an ARL or metal barrier layer 15. Thus, a method is needed that provides good adhesion between a low k dielectric layer and adjacent layers such as an ARL layer and a barrier metal layer.
Another concern with etch stop layer 13 is that its CMP rate is too high which causes an oxide recess 19 around the bond pad used for the polishing as shown in FIG. 3. An uneven surface surrounding the metal layer 16 is not tolerable. For example, subsequent layers that are formed on metal layer 16 will not be planar. In the case of patterning an uneven photoresist layer, the process latitude is likely to be too small to be useful in manufacturing. Therefore, it is desirable to incorporate a method for forming a damascene structure that will prevent an oxide recess adjacent to the metal layer during a CMP step.
Furthermore, because of the poor resistance of layer 13 to CMP, there is a tendency to form scratches 18 in layer 13 that may extend into low k dielectric layer 12. These are serious defects that can result in substrate 10 being scrapped or reworked which leads to a higher cost of device production.
Three related patents describe methods for repairing damage caused by etching a via hole through a low k dielectric layer consisting of carbon containing SiO2 or following a plasma etch removal of a photoresist layer on this dielectric layer. In each case, reactive Si sites are formed when Si—C bonds are broken during the etch process. These sites are sensitive to water and can form Si—OH bonds that later cleave during an annealing process. The presence of water in the via interferes with a subsequent metal deposition step. In U.S. Pat. No. 6,346,490, a plasma treatment with N2 and CH4 after an etch step is believed to reform Si—C bonds that prevent water uptake. Likewise, in U.S. Pat. No. 6,028,015, a H2 plasma treatment forms Si—H bonds at reactive Si sites. In U.S. Pat. No. 6,114,259, exposed vertical surfaces of the dielectric layer in a via hole are treated with a N2 plasma to densify the layer prior to a mild removal of a photoresist masking layer with H2O vapor plasma.